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NXP Semiconductors /LPC408x_7x /USB /I2C_CLKLO

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Interpret as I2C_CLKLO

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CDLO0RESERVED

Description

I2C Clock Low

Fields

CDLO

Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data